1. Field of the Invention
The present invention relates to digital filters and, more particularly, to a decimation filter for transforming a signal sampled at a certain sampling frequency into a signal at a lower sampling frequency.
2. Description of the Prior Art
One existing decimation filter transforms a 1-bit digital signal obtained through delta-sigma modulation at a certain sampling frequency, e.g., 64 fs (1 fs=44.1 kHz) into a 32-bit digital signal at a lower sampling frequency, e.g., 8 fs. Such a decimation filter, in particular, an FIR type filter has a configuration as shown in FIG. 1 in which 128 items of 1-bit input data are temporarily stored in input data storing means 1; pairs of the input data are sequentially supplied to calculation means 2 according to an operating clock at a frequency higher than 64 fs, e.g., an operating clock at 512 fs to perform product-sum calculations using filter coefficients sequentially output by coefficient storing means 3; and results of the calculation are output according to an operating clock at 8 fs.
For example, the filter coefficients stored in the coefficient storing means 3 are of an even order and symmetric in that the same filter coefficient is provided for items of input data which are symmetric about the center of the 128 items of input data (which are represented by H(1) through H(128) in FIGS. 2A and 2B) as shown in the filter coefficient C in FIGS. 2A and 2B. That is, 64 filter coefficients are stored in the coefficient storing means 3. Let us assume that the (−i)-th item of input data (for example, when the (−i)-th data is the newest item of data, the item preceding the (−i)-th item is the (−1−i)-th item) is referred to as “input data a−i. Then, the input data is calculated using the same filter coefficient that is used for the (−128+i−1)-th item of input data, i.e., input data a−128+i−1.
The filter calculations at the calculation means 2 are performed as follows in accordance with an operating clock at 512 fs. The input data storing means 3 sequentially outputs the input data a−i and input data a−128+i−1 to the calculation means 2 as a pair of input data. A pre-adder 21 in the calculation means 2 adds states “1” in each of the pairs of input data from the input data storing means 3 as “+1” and adds states “0” as “−1”. The coefficient storing means 3 sequentially outputs filter coefficients, and a multiplier 22 multiplies each of the results of calculation from the pre-adder 21 by each of the filter coefficients from the coefficient storing means 3. Each filter coefficient is comprised of one bit representing a sign and 24 bits representing a decimal part, and the multiplier 22 performs a multiplication of 1 bit×24 bits and switches the sign according to a sign bit of each of the pre-adder 21 and coefficient storing means 3. A post-adder 23 adds each of the results of calculation at the multiplier 22 and data held in a 32-bit shift register 24. Thus, a cumulative value of the results of multiplication at the multiplier 22 is held in the register 24. When the product-sum calculation according to the operating clock at 512 fs is performed 64 times, the data in the register 24 are output according to an operating clock at 8 fs to clear the contents of the register 24. A 32-bit digital signal at 8 fs is output from the calculation means 2 by repeating such an operation.
However, folding noises appear in audio signal bands at 20 kHz or less because of bands of approximately ±20 kHz about frequencies that are integral multiples of the decimated frequency. (e.g., 8 fs, 16 fs, 24 fs, 32 fs, 40 fs, and 48 fs in the case of a decimated frequency of 8 fs as in FIG. 1.) In the case of the decimation filter shown in FIG. 1, the filter coefficients are determined such that attenuations of 100 dB or more can be achieved in all cutoff bands as shown in FIG. 3. In order to achieve higher attenuations, the order of filter coefficients used for filter calculations and bit precision of the same must be improved, which has resulted in an increase in the scale of a circuit.
The invention is aimed to reduce folding noises into signal bands without any increase in the scale of a circuit attributable to the order and bit precision of filter coefficients and to provide a decimation filter with which steeper cutoff characteristics can be achieved.